I. Field of the Disclosure
The technology of the disclosure relates generally to monolithic three-dimensional (3D) integrated circuits (IC) (3DICs) and components therewithin.
II. Background
Mobile communication devices have become common in current society. The prevalence of these mobile devices is driven in part by the many functions that are now enabled on such devices. Demand for such functions increases processing capability requirements and generates a need for more powerful batteries. Within the limited space of the housing of the mobile communication device, batteries compete with the processing circuitry. These and other factors contribute to a continued miniaturization of components and power consumption within the circuitry. Miniaturization of the components impacts all aspects of the processing circuitry including the transistors and other reactive elements in the processing circuitry. One miniaturization technique involves arranging integrated circuits in not just an x-y coordinate system, but also in a z-coordinate system. That is, current miniaturization techniques use three-dimensional (3D) integrated circuits (ICs) (3DICs) to achieve higher device packing density, lower interconnect delay, and lower costs. Currently, there are several techniques to manufacture or form 3DICs.
While miniaturization has received copious attention in the realm of circuit design, other designers remain focused on clock signals within the circuits. The clock signals may control or synchronize myriad operations of components within the circuit. When considering synchronization issues, the time of arrival of the clock signal becomes important. The longer the electrical path between the clock source and the destination, the longer it takes for the clock signal to arrive. This time delay is further impacted by the resistance-capacitance (RC) factor of the electrical conductor. The higher the resistance, the slower the clock signal travels.
When clock signals are used in 3DICs, there are currently two contemplated ways to route clock signals within the 3DIC. In a first solution, a single clock is used and passed to all layers of the 3DIC through one or more through silicon vias (TSVs). TSVs generally have a relatively high capacitance and a correspondingly high RC factor. The RC factor significantly slows the clock signal and produces unacceptably high clock skew (i.e., the difference in the arrival time between two sequentially—adjacent registers or components within the circuit) and induces unacceptable power consumption. Further, using additional TSVs and clock buffers to contain the clock skew imposes an unacceptable area penalty. In a second solution, separate clocks are provided on different levels of the 3DIC. The use of separate clocks forces the circuit to operate asynchronously because the circuit design cannot guarantee that the clocks operate synchronously. While many circuits are capable of functional behavior with asynchronous control, many communication circuits require synchronous operation. In addition, each clock tree may be responsible for consuming approximately thirty-forty percent (30-40%) of the total power consumption in a typical digital logic circuit and thus, multiple clocks are not a viable solution for many low power circuit designs.
The advent of monolithic 3DIC technology has replaced the TSV with monolithic intertier vias (MIVs) which have substantially lower RC factors. The existence of MIAs allows a monolithic 3DIC to operate synchronously, but the challenge remains to make sure that the clock skew between components is relatively small.